1. Field of the Invention
The present invention relates to a bus coupling information processing system for enabling a plurality of bus masters to achieve multiple access to system buses, and more particularly it is applicable to system buses slow in input/output (I/O) access, such as in personal computers.
2. Description of the Prior Art
In a bus coupling information processing system of this kind according to the prior art, a certain bus master device connected to system buses, such as a central processing unit (CPU) or a direct memory access controller (DMAC), first issues a bus request signal to the system buses when data are to be transferred to a slave device, for instance a memory or some other I/O device. Upon gaining ownership of the system buses for that bus request signal, the bus master device owns the system buses to transfer data to the slave device. This ownership continues until the completion of the data transfer. Therefore, if the slave device takes a long access time, the bus master device will exclusively own the system buses all the time until a reply comes from the slave device.
Thus, this prior art involves the problem that the system buses remain owned by a specific bus master device until a data transfer to that bus master device is completed, obliging any other access to wait all that while. There further is the problem that during this period of waiting for a reply, more specifically during the access time for the data transfer, the system buses are not actually used, resulting in inefficient use of the system buses.
An object of the present invention is to obviate the aforementioned exclusive ownership of the system bus by a specific bus master device and thereby to improve the efficiency of system bus use.